Join us for an insightful virtual webinar on “The Engineer’s Guide to AI Strategy: Bridging the Gap Between Business and Technical Reality” hosted by the IEEE Women in Engineering Oregon Section AG and co-hosted by Spokane Section, Seattle Section San Francisco section, Santa Clara Valley Section, and San Fernando Valley Section WIE AG where we challenge the traditional boundaries between strategy, governance, and engineering. The rapid rise of Artificial Intelligence has led to countless “Proof of Concepts” that never make it to production—and production systems that fail spectacularly when they do. Why does this happen? A key reason lies in how organizations traditionally separate Strategy and Governance from Engineering execution. Strategy is often treated as a conceptual exercise, while governance is reduced to compliance checklists—leaving engineers disconnected from the very decisions that shape successful AI systems. In this insightful session, we challenge that paradigm. We will explore how engineers must evolve from execution-focused contributors to strategic decision-makers, integrating governance and strategy as core technical requirements in AI system design. Participants will learn how to bridge the gap between business vision and engineering reality by embedding strategy, governance, and ethical considerations directly into the development lifecycle. Additionally, the session will highlight practical strategies for women in tech to strengthen their influence—through confident communication, strategic thinking, and authentic leadership. Key Learning Objectives – Understand why many AI systems fail to transition from concept to production – Learn how to align engineering decisions with organizational strategy – Explore how to embed governance and safety into AI pipelines – Develop a strategic engineering mindset – Gain practical insights on influencing effectively as a woman in technology Who Should Attend – Engineers and AI practitioners – Early-career professionals and students – Technical leaders and project managers – Anyone interested in AI strategy, governance, and leadership development Speaker(s): Kierra Dotson Agenda: – Welcome & Overview of IEEE WIE Oregon Section Affinity Group – Invited talk from Kierra Dotson – Q/A Session Virtual: https://events.vtools.ieee.org/m/553802

Abstract: Nowadays, both digital and analog electronics are reaching fundamental limits that will require revolutionary approaches to satisfy the power/bandwidth requirements of the next generation of data-driven applications. In the first part of the talk, analog and digital signal processing will be compared in terms of power efficiency by highlighting the presence of a thermodynamic upper-bound which relates dynamic range, bandwidth and power dissipation. To circumvent this limit, in the second part of the talk, the quantized-analog signal processing will be introduced. In such approach, analog and digital domains are merged together in a more fluid scenario compared to traditional mixed-signal circuits avoiding the needs of rigid interfaces such as analog-to-digital and digital-to-analog converters. It will be shown that the quantized-analog signal processing leads to superior power efficiency and flexibility compared to its analog counterpart and it represents a good candidate for the development of a new generation of mixed signal integrated circuits. The effectiveness of the proposed solutions will be demonstrated through simulations and measurement results. Antonio Liscidini received the Laurea (summa cum laude) and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 2002 and 2006, respectively. He was a summer Intern with National Semiconductors, Santa Clara, CA, USA, in 2003, studying poly phase filters and CMOS low-noise amplifiers. From 2008 to 2012, he was an Assistant Professor with the University of Pavia and a consultant with Marvell Semiconductors, Pavia, in the area of integrated circuit design. In 2012, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, where he is currently Full Professor and Associate Chair Graduate. From 2019 to 2022 he was consultant for Huawei Technology Group in the area of RFIC for optical communication and SerDes. Since 2022 has been consultant for Marvell Technology group. His research interests are focused on analog mixed signal interfaces with particular emphasis on the implementations of transceivers and frequency synthesizers for wireless-wireline communication and ultra-low power applications. Dr. Liscidini was a recipient of the Best Student Paper Award at the IEEE 2005 Symposium on VLSI Circuits, co-recipient of the Best Invited Paper Award at the 2011 IEEE CICC and Best Student Paper Award at the 2018 IEEE ESSCIRC. He is currently Associate Editor in Chief for IEEE Transactions on Circuits and Systems II: Express Briefs. He has served as an Associate/Guest Editor for several IEEE Journal including: Open Journal of Solid-State Circuit Society, Transactions on Circuits and Systems II: Express Briefs and, Journal of Solid-State Circuits, RFIC Virtual Journal and Solid State Circuit Letters. He has been member for many TPC conferences including ISSCC, ESSCIRC, and CICC. Between 2016 and 2018, he has been a Distinguished Lecturer of the IEEE Solid-State Circuits Society. Since 2026, he is a IEEE Fellow. Speaker(s): Professor Antonio Liscidini, Room: Room 037, Bldg: Electrical and Computer Engineering Building, 185 W Stevens Wy NE , Seattle, Washington, United States, 98195

Title: Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation Abstract: Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration. Tetsuya Iizuka received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively. From 2007 to 2009, he was with THine Electronics Inc., Tokyo, as a High-Speed Serial Interface Circuit Engineer. He joined the University of Tokyo in 2009, where he is currently a Professor with the Department of Electrical Engineering and Information Systems, School of Engineering. From 2013 to 2015, he was a Visiting Scholar with the University of California at Los Angeles, Los Angeles, CA, USA. His current research interests include data conversion techniques, high-speed analog integrated circuits, digitally assisted analog circuits, and VLSI computer-aided design. He was a TPC member of ISSCC from 2013 to 2017 and CICC from 2014 to 2019. He is also serving as a member of the IEEE Asian Solid-State Circuits Conference (A-SSCC) and the IEEE VLSI Symposium on Circuits Technical Program Committees. Since 2025, he has been serving as a distinguished lecturer of the IEEE SSCS. Speaker(s): Tetsuya, Room: Room ECE 269, Bldg: Electrical and Computer Engineering Building, 185 Stevens Way, Seattle, Washington, United States, 98195